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Use of design pattern layout for automatic metrology recipe generation
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Paper Abstract

As critical dimension control requirements become more challenging, due to complex designs, aggressive lithography, and the constant need to shrink,metrology recipe generation and design evaluation have also become very complex. Hundreds of unique sites must be measured and monitored to ensure good device performance and high yield. The use of the design and layout for automated metrology recipe generation will be critical to that challenge. The DesignGauge from Hitachi implements a system enabling arbitrary recipe generation and control of SEM observations performed on the wafer, based only on the design information. This concept for recipe generation can reduce the time to develop a technology node from RET and design rule selection, through OPC model calibration and verification, and all the way to high volume manufacturing. Conventional recipe creation for a large number of measurement targets requires a significant amount of engineering time. Often these recipes are used only once or twice during mask and process verification or OPC calibration data acquisition. This process of manual setup and analysis is also potentially error prone. CD-SEM recipe creation typically requires an actual wafer, so the recipe creation cannot occur until the scanner and reticle are in house. All of these problems with conventional CD SEM lead to increased development time and reduced final process quality. The new model of CD-SEM recipe generation and management utilizes design-to-SEM matching technology. This new technology extracts an idealized shape from the designed pattern, and utilizes the shape information for pattern matching. As a result, the designed pattern is used as basis for the template instead of the actual SEM image. Recipe creation can be achieved in a matter of seconds once the target site list is finalized. The sequence of steps for creating a recipe are: generate a target site list, pass the design polygons (GDS) and site list to the CD SEM, define references, wafer map, and across wafer sampling, generate recipe. Utilizing this new technology, we can expect improved CD-SEM utilization and overall productivity defined by measurements acquired per unit time and by number of recipes that can be created. In addition, the control of recipe generation is improved as this automated data flow reduces the opportunities for errors. Finally, recipe creation automation can improve the time for production and development by enabling preparation before wafers get to the critical metrology steps. This is especially true in a development or foundry environment where the metrology recipe locations are updated frequently. A system is demonstrated where CDs and images can be acquired based on automated recipe generation, pattern recognition using the design polygons, and the measured CDís compared to the target CDís derived from the design. In addition, the presence of the design enables advanced information extraction such as edge placement error (EPE) in addition to traditional CD measurement. Example images and CD control analysis are presented for a critical resist inspection steps (poly, metal, and contact) and an etched poly pattern where an underlying layer is visible in SEM and used as part of the pattern matching template.

Paper Details

Date Published: 10 May 2005
PDF: 11 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.610663
Show Author Affiliations
Cyrus Tabery, Advanced Micro Devices. (United States)
Lorena Page, Hitachi High Technologies America, Inc. (United States)

Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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