An improved analysis of low frequency noise in ploy-Si TFT's is proposed in this paper. We present a simple parameter extraction method for 1/f noise sources in poly-Si TFT's based on a comprehensive model for noise generation. The sources for the low frequency noise are identified as the oxide traps in high current regime and the bulk traps in the grain boundary deletion region in low current regime. For high current regime, a simple and useful formula is developed from the Unified Model, which can be used for crystalline Si MOSFET's and SiGe MOSFET's also. For low current regime the bulk trap density in the grain boundary can be extracted utilizing the expression for the noise density considering the thermal activation of carriers from the traps which induces the fluctuations in the barrier height and hence the current noise. The extraction method is successfully applied to the experimental data from the literature with reasonable values for the noise parameters. The concept of mobility in poly-Si TFT's is elucidated. The work can also explain the experimental observation on the barrier height dependence of the low frequency drain current noise in poly-Si TFT's.

Date Published: 23 May 2005
PDF: 8 pages
Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); doi: 10.1117/12.609592

Published in SPIE Proceedings Vol. 5844:
Noise in Devices and Circuits III
Alexander A. Balandin; Francois Danneville; M. Jamal Deen; Daniel M. Fleetwood, Editor(s)