Share Email Print

Proceedings Paper

A simple noise modeling based testing of CMOS analog integrated circuits
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A technique for testing CMOS analog integrated circuits is presented which is based on an analysis of the noise behavior of the circuit under test (CUT). The technique is simple and new. The CUT in the present work is an integrated CMOS amplifier circuit designed in a standard 1.5 μm n-well CMOS process for operation at ±;2.5 V. The bridging faults simulating possible manufacturing defects have been introduced using fault injection transistors. The faults in the CUT are detected by observing the variation in the noise at the output of CUT, which is the sum of noise contributed from each component in the circuit. An analytical noise model of the CUT has been developed with and without faults and results are compared with the corresponding data obtained from the simulation studies using SPICE.

Paper Details

Date Published: 23 May 2005
PDF: 8 pages
Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); doi: 10.1117/12.609253
Show Author Affiliations
Siva Yellampalli, Louisiana State Univ. (United States)
Ashok Srivastava, Louisiana State Univ. (United States)

Published in SPIE Proceedings Vol. 5844:
Noise in Devices and Circuits III
Alexander A. Balandin; Francois Danneville; M. Jamal Deen; Daniel M. Fleetwood, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?