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Proceedings Paper

Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder
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Paper Abstract

In this paper we present the VLSI architecture for the buffer for tier-I of EBCOT encoder of JPEG2000. The buffer allows the integration of bit plane coder and arithmetic coder module employing concurrent symbol processing technique. The buffer architecture is optimized by exploiting the natural image statistics to optimally choose the buffer length parameter. The overall architecture is implemented using Altera FPGA and experimental results show a savings of 59% in the hardware cost with minimal reduction in the overall throughput.

Paper Details

Date Published: 30 June 2005
PDF: 8 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608585
Show Author Affiliations
Amit Kumar Gupta, Univ. of New South Wales (Australia)
Saeid Nooshabadi, Univ. of New South Wales (Australia)
Juan Montiel-Nelson, Univ. de Las Palmas de Gran Canaria (Spain)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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