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Proceedings Paper

Bounded budgeted parallel architecture versus control dominated architecture for hazard data-signal processor synthesis
Author(s): Bertrand Le Gal; Emmanuel Casseau; Eric Martin
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Paper Abstract

Multimedia applications such as video and image processing are often characterized by a large number of data accesses (i.e. RAM accesses). In many digital signal-processing applications, the array access patterns are regular and periodic. In these cases, optimized Pipelined Memory Access Controllers can be generated. This technique is used to improve the pipeline access mode to RAM by creating specialized hardware components for generating addresses and packing and unpacking data items. In this paper we focus on the design, implementation and validation of memory interfacing modules that can be automatically generated from a behavioural synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way. We also analyze the benefits of balancing dynamic address computations from datapath to specialized computation units placed in the memory controller, optimizing bitwise of operators and data locality i.e. reducing the power consumption.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608318
Show Author Affiliations
Bertrand Le Gal, Univ. of South Brittany (France)
Emmanuel Casseau, Univ. of South Brittany (France)
Eric Martin, Univ. of South Brittany (France)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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