Share Email Print

Proceedings Paper

Hardware implementation of the wavelet transform for JPEG2000
Author(s): J. Hormigo; J. M. Prades; J. Villalba; E. Zapata
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In this paper we shall propose and examine an VLSI architecture for the integer-to-integer wavelet transform which is used by JPEG2000 standard for lossless compression. In order to achieve a fully utilization of hardware resources independently of the bit-depth of the input data, on-line arithmetic (digit-serial computation) is proposed to carry out this architecture. Besides, a high throughput is achieved thanks to the high degree of parallelism that on-line arithmetic allows. The design has been simulated and implemented using Xilinx FPGA device, and its main results are provided.

Paper Details

Date Published: 30 June 2005
PDF: 11 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005);
Show Author Affiliations
J. Hormigo, Univ. of Malaga (Spain)
J. M. Prades, Univ. of Malaga (Spain)
J. Villalba, Univ. of Malaga (Spain)
E. Zapata, Univ. of Malaga (Spain)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?