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Proceedings Paper

Optical lithography technologies for 45-nm node CMOS
Author(s): Shoji Mimotogi; Fumikatsu Uesawa; Suigen Kyoh; Hiroharu Fujise; Eishi Shiobara; Mikio Katsumata; Hiroki Hane; Tomohiro Sugiyama; Koutaro Sho; Maki Miyazaki; Kazuhiro Takahata; Hideki Kanai; Kazuya Sato; Kohji Hashimoto
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Paper Abstract

In 45nm-node CMOS, the k1 value is around 0.35. In the low-k1 lithography, the robust design for lens aberration and process fluctuation such as mask CD error is required for manufacturing. The technologies of robust design for 45nm-node CMOS are proposed. The alternating phase shift mask has been applied to obtain high accurate CD controllability for gate level. Since the sensitivity to lens aberration is high, design rule is restricted. Immersion lithography with hyper NA over 1.0 is necessary for contact hole level to get large DOF margin. Since the mask enhanced error factor is large, high accurate CD uniformity on mask is necessary. Using hyper NA immersion tool, high density SRAM whose area is 0.25um2 can be clearly resolved.

Paper Details

Date Published: 12 May 2005
PDF: 8 pages
Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005); doi: 10.1117/12.600948
Show Author Affiliations
Shoji Mimotogi, Toshiba Corp. (Japan)
Fumikatsu Uesawa, Sony Corp. (Japan)
Suigen Kyoh, Toshiba Corp. (Japan)
Hiroharu Fujise, Toshiba Corp. (Japan)
Eishi Shiobara, Toshiba Corp. (Japan)
Mikio Katsumata, Sony Corp. (Japan)
Hiroki Hane, Sony Corp. (Japan)
Tomohiro Sugiyama, Sony Corp. (Japan)
Koutaro Sho, Toshiba Corp. (Japan)
Maki Miyazaki, Toshiba Corp. (Japan)
Kazuhiro Takahata, Toshiba Corp. (Japan)
Hideki Kanai, Toshiba Corp. (Japan)
Kazuya Sato, Toshiba Corp. (Japan)
Kohji Hashimoto, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 5754:
Optical Microlithography XVIII
Bruce W. Smith, Editor(s)

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