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Proceedings Paper

Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination
Author(s): Patrick K. Montgomery; Richard Peters; Cesar Garza Sr.; Jonathan Cobb; Bill Darlington; Colita Parker; Stan Filipiak; Danny Babbitt
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Paper Abstract

Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm. In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lithography process. As resist trim etch becomes more aggressive over time, LER on etched gates becomes less linked to the roughness in resist, and more to a product of the coupled lithography and etch processes. The aspect ratio of trimmed resist features increases and patterns become susceptible to pattern collapse, bending and tearing. Conversely if aspect ratios are maintained through the trim process, then the ability of the resist to protect the substrate from the final etch is degraded as the resist thickness decreases. A novel method of resist fluorination is presented that significantly reduces LER and pattern deformations such as collapse, tearing and bending. Experimental data shows that resist fluorination can make possible sub-30 nm etched polysilicon gates at aspect ratios on the order of 5:1. The same fluorination process yields LER improvements of 15% to 20% on average with largest improvements in the mid-range roughness frequencies of 10 - 50 μm-1. The length scale, or inverse of frequency, is also used in the study. The resist fluorination process is described as it is used in the study. Experimental and analytical data show how the process is reduced to practice and how LER and pattern deformation are improved. The fluorination process is simple to integrate into a standard wafer flow, has low cost of ownership, and yields large process improvements.

Paper Details

Date Published: 12 May 2004
PDF: 10 pages
Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (12 May 2004); doi: 10.1117/12.600785
Show Author Affiliations
Patrick K. Montgomery, Freescale Semiconductor Technology Solutions Organization (United States)
Richard Peters, Freescale Semiconductor Technology Solutions Organization (United States)
Cesar Garza Sr., Freescale Semiconductor, Inc. (United States)
Jonathan Cobb, Freescale Semiconductor Technology Solutions Organization (United States)
Bill Darlington, Freescale Semiconductor, Inc. (United States)
Colita Parker, Freescale Semiconductor Technology Solutions Organization (United States)
Stan Filipiak, Freescale Semiconductor, Inc. (United States)
Danny Babbitt, Freescale Semiconductor, Inc. (United States)

Published in SPIE Proceedings Vol. 5753:
Advances in Resist Technology and Processing XXII
John L. Sturtevant, Editor(s)

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