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Proceedings Paper

High accuracy 65nm OPC verification: full process window model vs. critical failure ORC
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Paper Abstract

It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.

Paper Details

Date Published: 12 May 2005
PDF: 12 pages
Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005); doi: 10.1117/12.600471
Show Author Affiliations
Amandine Borjon, Philips Semiconductors (France)
Jerome Belledent, Philips Semiconductors (France)
Shumay D. Shang, Mentor Graphics Corp. (United States)
Olivier Toublan, Mentor Graphics Corp. (United States)
Corinne Miramond, STMicroelectronics (France)
Kyle Patterson, Freescale Semiconductor (France)
Kevin Lucas, Freescale Semiconductor (France)
Christophe Couderc, Philips Semiconductors (France)
Yves Rody, Philips Semiconductors (France)
Frank Sundermann, STMicroelectronics (France)
Jean-Christophe Urbani, STMicroelectronics (France)
Stanislas Baron, STMicroelectronics (France)
Yorick Trouiller, LETI-CEA (France)
Patrick Schiavone, LETI-CEA (France)

Published in SPIE Proceedings Vol. 5754:
Optical Microlithography XVIII
Bruce W. Smith, Editor(s)

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