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Proceedings Paper

Surface engineering for resolution enhancement in nanoimprint lithography
Author(s): G. Y. Jung; W. Wu; Z. Li; S. Y. Wang; William M. Tong; R. Stanley Williams
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Paper Abstract

Nanoimprinting lithography was initiated as an alternative way to achieve nanoscale structures with high throughput and low cost. We have developed a UV-nanoimprint process to fabricate 34x34 crossbar circuits with a half-pitch of 50 nm (equivalent to a bit density of 10 Gbit/cm2). Our resist was of a single layer, which required fewer processing steps than any bi-layer process, but yielded high quality results. By engineering the surface energy of the substrate, we also eliminated the problem of trapped air during contact with the mold due to non-conformal contact such that it spreads the resist and expels trapped air. Resist adhesion to the gaps between features in the mold during mold separation is a challenge that becomes more severe as the pitch size shrinks. We have improved the resist adhesion to the substrate by applying a monolayer of surface linker molecule on the substrate surface. The surface linker bonded the resist to the substrate surface chemically and produced fine imprinted patterns at 30 nm hp.

Paper Details

Date Published: 6 May 2005
PDF: 5 pages
Proc. SPIE 5751, Emerging Lithographic Technologies IX, (6 May 2005); doi: 10.1117/12.599793
Show Author Affiliations
G. Y. Jung, Hewlett-Parkard Labs. (United States)
W. Wu, Hewlett-Parkard Labs. (United States)
Z. Li, Hewlett-Parkard Labs. (United States)
S. Y. Wang, Hewlett-Parkard Labs. (United States)
William M. Tong, Hewlett-Parkard Labs. (United States)
The Hewlett-Packard Co. (United States)
R. Stanley Williams, Hewlett-Parkard Labs. (United States)

Published in SPIE Proceedings Vol. 5751:
Emerging Lithographic Technologies IX
R. Scott Mackay, Editor(s)

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