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Proceedings Paper

Flexible alignment mark design applications using a next generation phase grating alignment system
Author(s): Paul Hinnen; Hyun-Woo Lee; Stefan Keij; Hiroaki Takikawa; Keita Asanuma; Kazutaka Ishigo; Tatsuhiko Higashiki
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Paper Abstract

In this paper, alignment and overlay results on processed short-flow wafers are presented. The impact of various mark designs on overlay performance was investigated, using a newly developed phase grating wafer alignment sensor concept. This concept is especially suited to support mark design flexibility, as well as to further improve upon the performance of the alignment sensors currently known. The unique sensor concept allows for alignment to a large variety of marks layouts, thereby complying with customer specific alignment mark design requirements. Here, we present alignment performance results on Toshiba's new marks. For this purpose, the new alignment sensor was integrated in an ASML proto-type tool. Alignment performance on ASML default mark types was demonstrated to guarantee backward compatibility with known alignment sensors. Alignment repeatability numbers of <3 nm (3sigma) were obtained for the different mark designs investigated. These numbers were measured on marks in resist as well as on processed short flow lots. Short term overlay capability of <6 nm (mean+3sigma) was demonstrated on Toshiba mark types, and on ASML mark types. Long term overlay values were demonstrated to be below 8 nm (mean + 3sigma) for both mark designs. The alignment and overlay capability, on processed wafers, was demonstrated for two process modules: Gate-to-Active (GC-AA) and Metal1-to-Contact (M1-CS). Typical overlay values measured were 20 to 30 nm, for the GC-AA and the M1-CS process module respectively. Further improvements with respect to alignment performance and overlay capability are anticipated through the use of advanced applications, and by further optimization of alignment mark design. This will be verified in future joint Toshiba/ASML experiments.

Paper Details

Date Published: 10 May 2005
PDF: 12 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.599494
Show Author Affiliations
Paul Hinnen, ASML. (Netherlands)
Hyun-Woo Lee, ASML (Netherlands)
Stefan Keij, ASML (Netherlands)
Hiroaki Takikawa, Hitachi High-Technologies (Japan)
Keita Asanuma, Semiconductor Co., Toshiba Corp. (Japan)
Kazutaka Ishigo, Semiconductor Co., Toshiba Corp. (Japan)
Tatsuhiko Higashiki, Semiconductor Co., Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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