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Proceedings Paper

Optimization of multi-step development scheme to improve the critical dimension uniformity
Author(s): Hsien-an Chang; Benjamin Szu-Min Lin; Kuei-Chun Hung; Shu-Ping Fang; Te-shao Hsu
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Paper Abstract

Tight control of critical dimensions (CDs) of integrated circuit (IC) is required to achieve desired circuit performances, and getting more and more important as the IC CD shrinks. Phenomena and solutions of inter-field and intra-field CD errors have been widely studied for years. One of the well-known intra-field CD errors is so called the developer micro-loading effect due to the different pattern density loadings across the exposure field, in the other words, the more different the pattern density is, the more CD errors it would be expected. Some of the circuit layouts, e.g. thick gate oxide layers of dual gate oxide processes, and gate layers of embedded memory products, have this kind of across field pattern density concerns because of the different pattern density areas. Some researches showed that eliminating the by-products during the development process could reduce the developer micro-loading effect. With a multi-step development process (Puddle-Static Development-Dry-Puddle-Static Development-Rinse/Dry), the by-products can be removed and achieve a better CD uniformity. In this paper, optimization of the first puddle time in the multi-step development process is found to be the most critical to achieve uniform intra-field CDs. The purpose of the first puddle step is not only to remove the by-products but also to control the influence of the by-products to achieve uniform intra-field CDs. Once most of the by-products generated during the whole development process were carried away by the first puddle step, the optimum static Dev. time is needed to obtain the minimum intra-field CD difference. However, different photo-resists with different chemical formulations are expected to have identical optimum puddle time due to different chemical reactions of each by-product species, e.g. i-line PRs vs DUV PRs, or annealing type DUV PRs vs acetel type DUV PRs. These comparisons will be explained in details in this paper. Finally, the source of the by-products during the developer process was also identified to verify the validation of the multi-step developer process.

Paper Details

Date Published: 17 May 2005
PDF: 9 pages
Proc. SPIE 5755, Data Analysis and Modeling for Process Control II, (17 May 2005); doi: 10.1117/12.599321
Show Author Affiliations
Hsien-an Chang, United Microelectronics Corp. (Taiwan)
Benjamin Szu-Min Lin, United Microelectronics Corp. (Taiwan)
Kuei-Chun Hung, United Microelectronics Corp. (Taiwan)
Shu-Ping Fang, United Microelectronics Corp. (Taiwan)
Te-shao Hsu, United Microelectronics Corp. (Taiwan)

Published in SPIE Proceedings Vol. 5755:
Data Analysis and Modeling for Process Control II
Iraj Emami, Editor(s)

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