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Proceedings Paper

Wafer current measurement for process monitoring
Author(s): Dmitry Shur; Alexander Kadyshevitch; Jeremy Zelenko; Carlos Mata; Victor Verdugo; Pierre-Yves Guittet; Brian Starr; Craig Duncan; Stefano Ventola; Jan Klinger
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Paper Abstract

Wafer Current Measurement (WCM) is an emerging technique for in-line process monitoring. A joint development project (JDP) has been conducted by Infineon Technologies and Applied Ma-terials (Process Diagnostics and Control Group). The main goal of this project was development of applications for the WCM technique in production environment and specifically for state of the art DRAM Infineon process. A new generation of SEM review tool with integrated FIB (Ap-plied SEMVision G2 FIB Defect Analysis system) was used for this work. A challenging layer approached in this work was the DTMO (Deep Trench Mask Open) which serves as a hard mask for subsequent deep trench (DT) capacitor formation in a silicon substrate. The aspect ratio of the openings in the DTMO layer can be as high as 20:1. As a result of the aggressive aspect ra-tio and sub-100 nm CDs the only available techniques for evaluating DTMO etch integrity (pos-sible under-etch and/or bottom CD variation) are destructive analysis methods. As a result of the extensive JDP, crucial yield limiting problems such as dielectric or/and stop layer under-etch as well as bottom CD violation have been revealed by the WCM in-line rather than by cross-sectioning in failure analysis laboratory or other destructive means. Besides, on the basis of bottom CD sensitivity of the WCM technique, etch chamber qualification (including matching and adjustment) feasibility was conducted. The motivation behind this is that chamber qualification is essential to shorten cycle time. In production environment the WCM technique is targeted for two basic applications: process monitoring including excursion control and early etch process drift warning and in-line etch chamber qualification. WCM "pilot" has been performed in production after DTMO for four novel DRAM products with CD down to 70 nm.

Paper Details

Date Published: 10 May 2005
PDF: 10 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.598398
Show Author Affiliations
Dmitry Shur, Applied Materials (Israel)
Alexander Kadyshevitch, Applied Materials (Israel)
Jeremy Zelenko, Applied Materials (Israel)
Carlos Mata, Infineon Technologies AG (Germany)
Victor Verdugo, Infineon Technologies AG (Germany)
Pierre-Yves Guittet, Infineon Technologies AG (Germany)
Brian Starr, Infineon Technologies AG (Germany)
Craig Duncan, Infineon Technologies AG (Germany)
Stefano Ventola, Applied Materials (Germany)
Jan Klinger, Applied Materials (Germany)

Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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