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Proceedings Paper

Characterization of 100 micron thick positive photoresist on 300-mm wafers
Author(s): Warren W. Flack; Ha-Ai Nguyen; Elliott Capsuto; Kelly Abreau
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Paper Abstract

The widespread adoption of advanced packaging techniques is driven by device performance and chip form factor considerations. Flip chip packaging is currently growing at a thirty percent compound annual rate and it is expected that in the near future over sixty percent of all 300 mm wafers will be bumped. To ensure optimal productivity and cost of ownership it is imperative to provide lithographic equipment and materials that are optimized for these applications. Due to the constantly shrinking bump pitch, it is critical to show excellent CD uniformity across the entire 300 mm wafer surface for feature sizes as small as 70 microns. Flip chip packaging as well as Nanotechnology (MEMS) applications frequently use one or more very thick photoresist layers for electroplating applications. The plating levels require a photosensitive polymer material capable of coating, exposing and electroplating with conventional equipment and standard ancillary process chemicals. Additionally the process times for coating, baking, exposure and development must be considered since these impacts the overall cost of ownership of the lithography cell. For thick photoresist layers the sidewall profile, plating resistance and postplating stripability are important characteristics. This study will characterize a novel single coat, positive tone photoresist (ShinEtsu SIPR 7120-20) used in electroplating levels up to 100 μm thick on 300 mm wafers exposed with the Ultratech Spectrum 300e2 stepper and coated and developed with a Steag Hamatech Modutrack system. Process capability is determined by analyzing photoresist film thickness uniformity and critical dimension (CD) control across the wafer. Basic photoresist characterization techniques such as cross sectional SEM analysis are used to establish lithographic capabilities. This study shows excellent adhesion to copper with no surface treatment and no photoresist popping during exposure or post exposure bake (PEB). High aspect ratio, lead-free, solder structures were then electroplated using the optimized photoresist process to demonstrate photoresist durability and stripability.

Paper Details

Date Published: 4 May 2005
PDF: 12 pages
Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); doi: 10.1117/12.598208
Show Author Affiliations
Warren W. Flack, Ultratech, Inc. (United States)
Ha-Ai Nguyen, Ultratech, Inc. (United States)
Elliott Capsuto, Shin-Etsu MicroSi, Inc. (United States)
Kelly Abreau, STEAG Hamatech USA (United States)

Published in SPIE Proceedings Vol. 5753:
Advances in Resist Technology and Processing XXII
John L. Sturtevant, Editor(s)

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