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Proceedings Paper

Efficient mapping of the H.264 encoding algorithm onto multiprocessor DSPs
Author(s): Amit Gulati; George Campbell
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Paper Abstract

With the introduction of a variety of novel coding tools in H.264 has come an increase in complexity that few processor architectures can facilitate. Prior coding loops, such as MPEG-2, provided fewer variations and optional capabilities as a part of the standard implementation; and as such they were readily partitioned in an intuitive manner with little deviation. Induced by the need to scale to such high-complexity algorithms, homogenous multiprocessor architectures are becoming more common. H.264 poses with it several new options to the software architect in approaching the issue of partitioning the coding blocks most efficiently across a multiprocessor architecture. In this paper, we address issues that arise from the mapping of H.264 onto Multiprocessor DSP chips. We discuss aspects of algorithm partitioning, reference frame coherency, and synchronization issues. We show flexible methods for mapping the algorithm onto MDSPs which allow scalability over coding tools, resolutions, and computation/bandwidth availability.

Paper Details

Date Published: 8 March 2005
PDF: 10 pages
Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.593980
Show Author Affiliations
Amit Gulati, Cradle Technologies (United States)
George Campbell, Cradle Technologies (United States)

Published in SPIE Proceedings Vol. 5683:
Embedded Processors for Multimedia and Communications II
Subramania Sudharsanan; V. Michael Bove Jr.; Sethuraman Panchanathan, Editor(s)

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