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Proceedings Paper

Challenges for on-chip optical interconnects
Author(s): Kenneth C. Cadien; Miriam R. Reshotko; Bruce A. Block; Audrey M. Bowen; David L. Kencke; Paul Davids
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Paper Abstract

As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical building blocks will be reviewed. It will be shown that significant advances have been made in the design and fabrication of waveguides, detectors, and couplers. However, major challenges in high speed electrical to optical conversion and signaling remain.

Paper Details

Date Published: 7 March 2005
PDF: 11 pages
Proc. SPIE 5730, Optoelectronic Integration on Silicon II, (7 March 2005); doi: 10.1117/12.591163
Show Author Affiliations
Kenneth C. Cadien, Intel Corp. (United States)
Miriam R. Reshotko, Intel Corp. (United States)
Bruce A. Block, Intel Corp. (United States)
Audrey M. Bowen, Intel Corp. (United States)
David L. Kencke, Intel Corp. (United States)
Paul Davids, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 5730:
Optoelectronic Integration on Silicon II
Joel A. Kubby; Ghassan E. Jabbour, Editor(s)

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