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Proceedings Paper

Design of polarization-insensitive components using geometrical and stress-induced birefringence in SOI waveguides
Author(s): Dan-Xia Xu; Winnie N. Ye; Alexei Bogdanov; Dan Dalacu; Andre Delage; Pavel Cheben; Siegfried Janz; Boris Lamontagne; Marie-Josee Picard
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Paper Abstract

We review the use of the oxide cladding stress induced photoelastic effect to eliminate the modal birefringence in silicon-on-insulator (SOI) ridge waveguide components, and highlight characteristics particular to high index contrast (HIC) systems. The birefringence in planar waveguides has its origin in the electromagnetic boundary conditions at the waveguide boundaries, and can be further modified by the presence of stress in the materials. It is shown that geometrical constraints imposed by different design and fabrication considerations become increasingly difficult to satisfy with decreasing core sizes. On the other hand, with typical stress levels of -100 MPa to -400 MPa (compressive) in SiO2 used as the upper cladding, the effective indices are altered up to the order of 10-3 for ridges with heights ranging from 1 μm to 5 μm. We demonstrate that the stress can be effectively used to balance the geometrical birefringence. Birefringence-free operation is achieved for waveguides with otherwise large birefringence by using properly chosen thickness and stress of the upper cladding layer. This allows the waveguide cross-section profiles to be optimized for design criteria other than zero-birefringence. Since the index changes induced by the stress are orders of magnitude smaller than the waveguide core/cladding index contrast, changes in the mode profiles are insignificant and the associated mode mismatch loss is negligible. We study the stress-induced effects in two parallel waveguides of varying spacing, to emulate the condition in directional couplers and ring-resonators. In the arrayed waveguide grating (AWG) demultiplexers fabricated in the SOI platform, we demonstrated the reduction of the birefringence from 1.3x10-3 (without the upper cladding) to below 1x10-4 across the spectral band by using a 0.6 μm oxide upper cladding with a stress of -320 MPa (compressive). Design options for relaxed dimensional tolerance and improved coupler performance made available by using stress engineering are discussed.

Paper Details

Date Published: 7 March 2005
PDF: 15 pages
Proc. SPIE 5730, Optoelectronic Integration on Silicon II, (7 March 2005); doi: 10.1117/12.589158
Show Author Affiliations
Dan-Xia Xu, National Research Council Canada (Canada)
Winnie N. Ye, National Research Council Canada (Canada)
Alexei Bogdanov, National Research Council Canada (Canada)
Dan Dalacu, National Research Council Canada (Canada)
Andre Delage, National Research Council Canada (Canada)
Pavel Cheben, National Research Council Canada (Canada)
Siegfried Janz, National Research Council Canada (Canada)
Boris Lamontagne, National Research Council Canada (Canada)
Marie-Josee Picard, National Research Council Canada (Canada)

Published in SPIE Proceedings Vol. 5730:
Optoelectronic Integration on Silicon II
Joel A. Kubby; Ghassan E. Jabbour, Editor(s)

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