
Proceedings Paper
Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architectureFormat | Member Price | Non-Member Price |
---|---|---|
$17.00 | $21.00 |
Paper Abstract
Consumer electronics products are multi-functional devices that combine a set of media applications. Media data in such products is largely processed in heterogeneous multiprocessor subsystems that are integrated into a system on chip (SoC). A product engineer configures each subsystem for a collection of predefined applications when deploying the SoC in a product. Oftentimes, the system supports a large number of desired application configurations, or 'use cases’. The system moves from one configuration to the next by adapting the configuration of a running application, referred to as 'dynamic reconfiguration’. This paper presents a practical approach to dynamic application reconfiguration in a heterogeneous multiprocessor subsystem. The targeted media applications are constructed as a graph of concurrently executing interconnected tasks that exchange information through streams of data. Configuring such a streaming graph entails the instantiation and interconnection of tasks, setting of task parameters, assignment of tasks to coprocessors, and the allocation of communication buffers in memory. The paper derives a reconfiguration interface that can be supported in hardware, yet isolates application configuration knowledge from the coprocessor hardware. Though simple and easy to use, the interface addresses the key challenge of reconfiguring individual tasks while maintaining real-time behavior and data integrity of the overall set of concurrently executing applications.
Paper Details
Date Published: 8 March 2005
PDF: 11 pages
Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.586112
Published in SPIE Proceedings Vol. 5683:
Embedded Processors for Multimedia and Communications II
Subramania Sudharsanan; V. Michael Bove Jr.; Sethuraman Panchanathan, Editor(s)
PDF: 11 pages
Proc. SPIE 5683, Embedded Processors for Multimedia and Communications II, (8 March 2005); doi: 10.1117/12.586112
Show Author Affiliations
Martijn J. Rutten, Philips Semiconductors (Netherlands)
Evert-Jan Pol, Philips Semiconductors (Netherlands)
Jos van Eijndhoven, Philips Research Labs. (Netherlands)
Evert-Jan Pol, Philips Semiconductors (Netherlands)
Jos van Eijndhoven, Philips Research Labs. (Netherlands)
Karel Walters, Philips Research Labs. (Netherlands)
Gerben Essink, Philips Research Labs. (Netherlands)
Gerben Essink, Philips Research Labs. (Netherlands)
Published in SPIE Proceedings Vol. 5683:
Embedded Processors for Multimedia and Communications II
Subramania Sudharsanan; V. Michael Bove Jr.; Sethuraman Panchanathan, Editor(s)
© SPIE. Terms of Use
