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Proceedings Paper

SCORPIUS algorithm benchmarks on the image understanding architecture machine
Author(s): Julius F. Bogdanowicz; J. Gregory Nash; David B. Shu
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Paper Abstract

Many Hughes tactical and strategic programs need high performance image processing. For example, photo-interpretation applications can require up to four orders of magnitude speedup over conventional computer architectures. Therefore, parallel processing systems are needed to help close the processing gap. Vision applications can usually be decomposed into three levels of processing called high, intermediate, and low level vision. Each processing level typically requires different types of numeric/symbolic computation, processing task granularities, and communications bandwidths. No parallel processing system is commercially available that is optimized for the entire range of computations. To meet these processing challenges, the image understanding architecture (IUA) has been developed by Hughes in collaboration with the University of Massachusetts. The IUA is a heterogeneous, hierarchical, associative parallel processor that is organized in three levels corresponding to the vision problem. Its lowest level consists of a large content addressable array parallel processor. This array of 'per pixel' bit serial processors is used for fixed point, low level numeric, and symbolic computations. The middle level is an interface communications array processor (ICAP). ICAP is an array of digital signal processing chips from TI TMS320Cx line, used for high speed number crunching. The highest level is the symbolic processing array. It is an array of general purpose microprocessors in which the artificial intelligence content of the image understanding software resides. A set of benchmarks from the DARPA/ORD sponsored SCORPIUS program were developed using the IUA. The set of algorithms included low level image processing as well as high level matching algorithms. Benchmark performance on the second generation IUA hardware is over four orders of magnitude faster than equivalent algorithms implemented on a DEC VAX 8650. The first generation hardware is operational. Development of the second generation hardware and software for DARPA's Unmanned Ground Vehicle Program is under way in collaboration with the University of Massachusetts and Amerinex Artificial Intelligence.

Paper Details

Date Published: 1 April 1992
PDF: 1 pages
Proc. SPIE 1623, The 20th AIPR Workshop: Computer Vision Applications: Meeting the Challenges, (1 April 1992);
Show Author Affiliations
Julius F. Bogdanowicz, Hughes Aircraft Co. (United States)
J. Gregory Nash, Hughes Aircraft Co. (United States)
David B. Shu, Hughes Aircraft Co. (United States)

Published in SPIE Proceedings Vol. 1623:
The 20th AIPR Workshop: Computer Vision Applications: Meeting the Challenges
Joan B. Lurie, Editor(s)

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