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Proceedings Paper

Device analysis: a way to reduce patterning cost at mask and wafer level?
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Paper Abstract

Preserving the accuracy of pattern reproduction on silicon with the decreasing linewidth usually requires paying increasingly higher prices for the masks. However, the advances in optical, device and circuit simulation tools are offering interesting alternatives to the tightening of reticle specifications. The performance of the next generation circuits can be verified by integrated simulation at the mask, device, and cell level. The tradeoff between mask quality, process options, product characteristics, and manufacturing cost can be thereby analyzed. Such integrated simulation impacts also mask shop and process deliverables. As an example, it was shown the potential to reduce reticle rejection rate by several times. In this work, integrated simulation helped choose the most economical option for the poly mask process, to control channel CD variation related to the discontinuity of gate pattern in multi-transistor memory cells. We evaluated the tradeoff between cell performance and the cost of the phase shift mask set to reduce poly CD variation. Based on the cell stability dependence on photo process parameters, we proved that the low cost approach can still yield economically satisfactory results.

Paper Details

Date Published: 6 December 2004
PDF: 8 pages
Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); doi: 10.1117/12.569904
Show Author Affiliations
Artur P. Balasinski, Cypress Semiconductor Corp. (United States)
Frank A.J.M. Driessen, Takumi Technology (Netherlands)

Published in SPIE Proceedings Vol. 5567:
24th Annual BACUS Symposium on Photomask Technology
Wolfgang Staud; J. Tracy Weed, Editor(s)

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