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Proceedings Paper

LER characterization and impact on 0.13-µm lithography for OPC modeling
Author(s): Peter Nikolsky; Rama Tweg; Enna Altshuler; Eitan N. Shauly
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Paper Abstract

This paper presents Line Edge Roughness (LER) characterization for Tower Semiconductor 0.13um Standard Logic technology with advanced OPC modeling. First the applicability of top-view CD-SEM and AFM for LER measurement of poly-Si transistor gate characterization is studied. Then the influence of aerial image contrast and the gradient of the photoactive component on LER is reviewed and the possibility of minimizing LER by optimizing process conditions is considered. Finally the impact of LER on OPC model accuracy is reviewed. Model predictability with and without LER taken into account is compared.

Paper Details

Date Published: 6 December 2004
PDF: 9 pages
Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); doi: 10.1117/12.568999
Show Author Affiliations
Peter Nikolsky, Tower Semiconductor Ltd. (Israel)
Rama Tweg, Tower Semiconductor Ltd. (Israel)
Enna Altshuler, Tower Semiconductor Ltd. (Israel)
Eitan N. Shauly, Tower Semiconductor Ltd. (Israel)

Published in SPIE Proceedings Vol. 5567:
24th Annual BACUS Symposium on Photomask Technology
Wolfgang Staud; J. Tracy Weed, Editor(s)

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