Share Email Print

Proceedings Paper

The guideline of reticle data management (Ver. 2)
Author(s): Nobuyuki Iriki; Norihiko Miyazaki; M. Homma; T. Sato; Toshio Onodera; T. Matsuda; T. Uga; Hidehiro Higashino; Iwao Higashikawa; Nobuyuki Yoshioka
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

We reported the Guideline (Ver.1) of Reticle Data Management (RDM) Activity in 2001. While focusing on SoC (System on Chip) business, we have improved the efficiency in design technology, mask manufacturing and wafer manufacturing. Especially, these subjects have been the lithography costs including a reticle cost, a shorter life cycle of products, more difficult techniques, a lower cost and shorter total TAT from design to chip shipping. The Guideline Ver1.0 announced the standardization of interface contents from design to mask manufacture, and to wafer manufacture as well. According to the Guideline Ver2 in 2003, RDM activity has developed the optimization of a new engineering chain management that added the pattern data and the linkage to EDA. The unique characteristics of standardization proposed in Ver2 is that apart from standardization of the data format of the pattern data itself, expression of referencing pattern data and other additional information that are associated in case pattern data is utilized should be standardized. The difference between "expression" and "format" could be understood. These expressions include knowledge, view, property for retrieve, annotation, reference and relation about pattern data. These relations will be considered from a user's view of utilizing pattern data. The purpose of this expressions is to combine various standards relating to reticle. For example the linkage between RDM and UDM that is standardization of a data model relating to EDA tools and their applications is assumable. These two layers of standardization will make creative associations of applications possible.

Paper Details

Date Published: 2 June 2004
PDF: 10 pages
Proc. SPIE 5504, 20th European Conference on Mask Technology for Integrated Circuits and Microcomponents, (2 June 2004); doi: 10.1117/12.568028
Show Author Affiliations
Nobuyuki Iriki, JEITA (Japan)
Renasas (Japan)
Norihiko Miyazaki, JEITA (Japan)
Fujitsu (Japan)
M. Homma, JEITA (Japan)
NECEL (Japan)
T. Sato, JEITA (Japan)
Toshiba Corp. (Japan)
Toshio Onodera, JEITA (Japan)
Oki Electric Industry Co., Ltd. (Japan)
T. Matsuda, JEITA (Japan)
Sanyo (Japan)
T. Uga, JEITA (Japan)
ROHM (Japan)
Hidehiro Higashino, JEITA (Japan)
Oki Electric Industry Co., Ltd. (Japan)
Iwao Higashikawa, JEITA (Japan)
SELETE (Japan)
Nobuyuki Yoshioka, JEITA (Japan)
SELETE (Japan)

Published in SPIE Proceedings Vol. 5504:
20th European Conference on Mask Technology for Integrated Circuits and Microcomponents
Uwe F. W. Behringer, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?