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Proceedings Paper

Chip-scale thermal management of high-brightness LED packages
Author(s): Mehmet Arik; Stanton Weaver
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Paper Abstract

The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of localized hot spots at the chip active layer. The importance of “zero defects” in one of the more popular interconnect schemes; the “epi down” soldered flip chip configuration is investigated and demonstrated.

Paper Details

Date Published: 20 October 2004
PDF: 10 pages
Proc. SPIE 5530, Fourth International Conference on Solid State Lighting, (20 October 2004); doi: 10.1117/12.566061
Show Author Affiliations
Mehmet Arik, GE Global Research Ctr. (United States)
Stanton Weaver, GE Global Research Ctr. (United States)

Published in SPIE Proceedings Vol. 5530:
Fourth International Conference on Solid State Lighting
Ian T. Ferguson; Nadarajah Narendran; Steven P. DenBaars; John C. Carrano, Editor(s)

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