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Proceedings Paper

Regularities of power consumption in quasi-adiabatic logical gates
Author(s): Vladimir V. Losev; Victor I. Staroselsky
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Paper Abstract

Power consumption regularities of the most perspective quasi-adiabatic base logic gates are investigated by method of computer modeling. The effect of abnormal high power consumption in a range of low frequencies is discovered and explained; the method of its neutralization is offered. It is revealed, that in a range of high frequencies energy dissipation in gates decreases at reduction of clock frequency more poorly, than under the law 1 / f . The mechanism of this anomaly is found out. The established laws a power consumption of the base logic gates allow to choose the compromise between power consumption and speed, optimize power characteristics of base gates. It's also allowed to predict their improvement at quality improvement of technology.

Paper Details

Date Published: 28 May 2004
PDF: 12 pages
Proc. SPIE 5401, Micro- and Nanoelectronics 2003, (28 May 2004); doi: 10.1117/12.562669
Show Author Affiliations
Vladimir V. Losev, Moscow State Institute of Electronic Technology (Russia)
Victor I. Staroselsky, Moscow State Institute of Electronic Technology (Russia)

Published in SPIE Proceedings Vol. 5401:
Micro- and Nanoelectronics 2003
Kamil A. Valiev; Alexander A. Orlikovsky, Editor(s)

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