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Proceedings Paper

Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology
Author(s): K. Honda; K. Peter; Y. Zhang; B. Yu; K. Park; Xiaolei Li; K. Michaels; Shinichi Yamada; T. Noguchi
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Paper Abstract

With downscaling of dimensions, essential challenges on layout printability significantly increase. The design rule cannot be shrunk with linearity any more. Historically, in the early development stage, simple test patterns like snake/comb or border/borderless via chains were used for identifying design and process issues electrically. However it is unclear how much these patterns represent the sensitive patterns for the real critical failures. The lack of these kinds of critical patterns would always cause yield problems in the volume production. In this paper, we show the result of evaluating 65-nm BEOL process by using the test patterns that can cover critical layout situations. Especially, it was focused on the line end via hole, which is believed to cause the systematic yield degradation. The key steps in our process/design decomposition methodology are design attribute and process space analysis. By exploring the process space for a given design, the method allows to find the most challenging patterns to print due to various process issues. The test patterns were generated from critical pattern extracted from standard cells library by considering our preliminary opc and mask design flow. Simulation of all test patterns are performed to ensure that DOE range is sufficient to cover the entire process/design space. These patterns are generated from the 65nm node ground design rule. It used a size of 90nm as metal minimum width and space, and a size of 100nm for fixed via hole diameter. It was confirmed by simulations that all the test pattern represent for the original design on each module process/design space. All the test patterns were measured by the standard parametric e-test setup. The amount of line end pull back can be inferred from the via resistance, and the amount of line end widening can be inferred from the leakage current between via chains and neighboring lines. Thus the meaningful information about the OPC and litho process can be obtained quickly without extensive use of SEM measurements. More than 200 test patterns considering logic randomness were designed and fabricated by using 65-nm node BEOL process. We found that 50nm or more line extension is necessary to suppress the pull back issue caused by the defocus effect. To prevent the metal short of the isolated pattern next to or surrounding by the wide metal, the minimum space with wide neighboring metal was defined. Using this methodology, our 65-nm design rule has been successfully evaluated and optimized.

Paper Details

Date Published: 3 May 2004
PDF: 8 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.544234
Show Author Affiliations
K. Honda, Toshiba Corp. (Japan)
K. Peter, PDF Solutions Inc. (United States)
Y. Zhang, PDF Solutions Inc. (United States)
B. Yu, PDF Solutions Inc. (United States)
K. Park, PDF Solutions Inc. (United States)
Xiaolei Li, PDF Solutions Inc. (United States)
K. Michaels, PDF Solutions Inc. (United States)
Shinichi Yamada, Toshiba Corp. (Japan)
T. Noguchi, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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