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Proceedings Paper

Feature level test patterns for characterizing residual process effects
Author(s): Andrew R. Neureuther; Gregory R. McIntyre; Frank E. Gennari; Michael Lam; Jason P. Cain; Garth C. Robins; Edward Huang; Jihong Choi; Ling Wang; Lei Yuan; Hideaki Oshima
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Paper Abstract

Layout test patterns are being pursued that are more sensitive than circuit patterns in detecting and quantifying residual processing effects. These patterns permit the rapid searching of layouts for the locations of worst-case process impacts, and may facilitate layout compensation at OPC speeds. These patterns have been taped-out along with snippets of circuits in preparation for experimental verification of the ability to link residual process effects to electronic design. The collection includes pattern-and-probe-based targets for measuring aberrations, illumination non-uniformity and etch-depth errors in phase-shifting masks, plasma etching with loading effects related to area and perimeter factors, and patterns for CMP orientation and feature proximity. The goal is to use these test patterns to develop maximum lateral impact functions for each individual process effect for use in fast-CAD techniques capable of inspecting large layouts.

Paper Details

Date Published: 3 May 2004
PDF: 9 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.540685
Show Author Affiliations
Andrew R. Neureuther, Univ. of California/Berkeley (United States)
Gregory R. McIntyre, Univ. of California/Berkeley (United States)
Frank E. Gennari, Univ. of California/Berkeley (United States)
Michael Lam, Univ. of California/Berkeley (United States)
Jason P. Cain, Univ. of California/Berkeley (United States)
Garth C. Robins, Univ. of California/Berkeley (United States)
Edward Huang, Univ. of California/Berkeley (United States)
Jihong Choi, Univ. of California/Berkeley (United States)
Ling Wang, Univ. of California/Berkeley (United States)
Lei Yuan, Univ. of California/Berkeley (United States)
Hideaki Oshima, Univ. of California/Berkeley (United States)


Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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