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Proceedings Paper

A half D1 MPEG-4 encoder on the BSP-15 DSP
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Paper Abstract

In this paper, we present the work on implementation of a half-D1interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel procesing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ~2Mbps.

Paper Details

Date Published: 18 January 2004
PDF: 5 pages
Proc. SPIE 5308, Visual Communications and Image Processing 2004, (18 January 2004); doi: 10.1117/12.538252
Show Author Affiliations
Lulin Chen, Sarnoff Corp. (United States)
Zhihai He, Univ. of Missouri/Columbia (United States)
Chang Wen Chen, Florida Institute of Technology (United States)
Michael A. Isnardi, Sarnoff Corp. (United States)

Published in SPIE Proceedings Vol. 5308:
Visual Communications and Image Processing 2004
Sethuraman Panchanathan; Bhaskaran Vasudev, Editor(s)

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