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Proceedings Paper

Combining OPC and design for printability into 65-nm logic designs
Author(s): Kevin D. Lucas; Chi-Min Yuan; Robert Boone; Kirk Strozewski; Jason Porter; Ruiqi Tian; Karl Wimmer; Jonathan Cobb; Bill Wilkinson; Olivier Toublan
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Paper Abstract

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.

Paper Details

Date Published: 3 May 2004
PDF: 12 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.537655
Show Author Affiliations
Kevin D. Lucas, Motorola (France)
Chi-Min Yuan, Motorola (United States)
Robert Boone, Motorola (France)
Kirk Strozewski, Motorola (United States)
Jason Porter, Motorola (United States)
Ruiqi Tian, Motorola (United States)
Karl Wimmer, Motorola (France)
Jonathan Cobb, Motorola (United States)
Bill Wilkinson, Motorola (United States)
Olivier Toublan, Mentor Graphics Europe (France)

Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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