Share Email Print

Proceedings Paper

The application of CPL reticle technology for the 0.045-mm node
Author(s): Will Conley; Douglas J. Van Den Broeke; Robert John Socha; Wei Wu; Lloyd C. Litt; Kevin D. Lucas; Bernard J. Roman; Richard D. Peters; Colita Parker; Fung Chen; Kurt E. Wampler; Thomas L. Laidig; Erika Schaefer; Jan-Pieter Kuijten; Arjan Verhappen; Stephan van de Goor; Martin Chaplin; Bryan S. Kasprowicz; Christopher J. Progler; Emilien Robert; Philippe Thony
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Paper Details

Date Published: 28 May 2004
PDF: 6 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.537613
Show Author Affiliations
Will Conley, Motorola (United States)
Douglas J. Van Den Broeke, ASML (United States)
Robert John Socha, ASML (United States)
Wei Wu, Motorola (United States)
Lloyd C. Litt, Motorola (United States)
Kevin D. Lucas, Motorola (United States)
Bernard J. Roman, Motorola (United States)
Richard D. Peters, Motorola (United States)
Colita Parker, Motorola (United States)
Fung Chen, ASML (United States)
ASML (Netherlands)
Kurt E. Wampler, ASML (United States)
ASML (Netherlands)
Thomas L. Laidig, ASML (United States)
ASML (Netherlands)
Erika Schaefer, ASML (United States)
ASML (Netherlands)
Jan-Pieter Kuijten, ASML (United States)
ASML (Netherlands)
Arjan Verhappen, ASML (United States)
ASML (Netherlands)
Stephan van de Goor, ASML (United States)
ASML (Netherlands)
Martin Chaplin, ASML (United States)
ASML (Netherlands)
Bryan S. Kasprowicz, Photronics, Inc. (United States)
Christopher J. Progler, Photronics, Inc. (United States)
Emilien Robert, STMicroelectronics (France)
Philippe Thony, STMicroelectronics (France)

Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?