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Proceedings Paper

RET integration of CPL technology for random logic
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Paper Abstract

As IC fabrication processes are maturing for the 130nm node, IC devices manufacturers are focusing on 90nm device manufacturing at ever-lower k1 values. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at a similar k1 of near 0.3 using ArF. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique vs. the two masks and double exposure technique required for alternating phase shift masks (altPSM). The high mask cost of altPSM also discourages its use for low volume manufacturing. The two leading candidates candidates for 90nm node using KrF are: 6% attenuated PSM and CPL Technology. In this work, we present a methodology on how to use transmission tuning to achieve the best process latitude for patterning poly gate layer. First, we analyze the diffraction patterns from 6% attPSM and CPL mask features and identify the optimum transmission for various pitches. Next we describe how CPL mask can be used as a variable transmission attenuated mask to produce the best through pitch imaging performance and show a practical implementation method for applying to real device designs. Then we demonstrate how to integrate the optimized transmission tuning into the data process and OPC flow for generating CPL mask. Finally, we provide an example experimental result on a real device pattern.

Paper Details

Date Published: 28 May 2004
PDF: 17 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.537414
Show Author Affiliations
Stephen D. Hsu, ASML MaskTools, Inc. (United States)
Douglas J. Van Den Broeke, ASML MaskTools, Inc. (United States)
J. Fung Chen, ASML MaskTools, Inc. (United States)
Xuelong Shi, ASML MaskTools, Inc. (United States)
Michael Hsu, ASML MaskTools, Inc. (United States)
Thomas L. Laidig, ASML MaskTools, Inc. (United States)
Will Conley, Motorola, Inc. (United States)
Lloyd C. Litt, Motorola, Inc. (United States)
Wei Wu, Motorola, Inc. (United States)

Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

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