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Proceedings Paper

Impact of lithography variability on statistical timing behavior
Author(s): Christopher J. Progler; Amir Borna; David Blaauw; Pierre Sixt
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Paper Abstract

We describe a numerical model for chip level lithography variability analysis. Gate level critical dimensions are adjusted based on lithographic variability simulations and these perturbed gate lengths are input to a chip timing analyzer. Statistical modeling studies highlight the interaction between lithography variability and chip timing performance including the role of lithography error correlation length, optical proximity effect residuals, exposure system imperfections and photomask errors. Understanding these relationships is a critical building block for lithographic error tolerancing, design manufacturability improvement and lithography limited yield enhancements on integrated circuits for which timing is a key performance metric.

Paper Details

Date Published: 3 May 2004
PDF: 10 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.537259
Show Author Affiliations
Christopher J. Progler, Photronics Inc. (United States)
Amir Borna, Univ. of Michigan (United States)
David Blaauw, Univ. of Michigan (United States)
Pierre Sixt, Photronics Inc. (United States)


Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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