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Proceedings Paper

Yield-enhanced layout generation by new design for manufacturability (DfM) flow
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Paper Abstract

Design for manufacturability ( DfM ) flow consisting of a new lithography design approach at the design rule definition stage and manufacturability check at physical layout stage is proposed to clean up hot spots and guarantee the final layouts to be free of hot spots under low-k1 lithography condition. At the initial development stage, design rules ( DRs ), resolution enhancement technique ( RET ) and optical proximity correction ( OPC ) methods and critical dimension ( CD ) target and specification are determined by the new lithography design approach to reduce hot spots next-generation’s tentative layout made by the compactor. At the physical layout stage, a manufacturability check ( MC ) is essential to wipe out hot spots resulted from immaturity of DRs and process parameters fixed at the initial development stage by making three feedback approaches: the refinement of design rule, the repair of hot spots by designers and the refinement of OPC parameters and/or methods. Also, an alternative of layout modification or OPC improvement for cleaning hot spots are cleared by categorization of CD variation induced by some dose and focus conditions and an error of CD average for the target pattern. The proposed DfM flow is found to be highly effective for the robust pattern formation under the low-k1 lithography condition.

Paper Details

Date Published: 3 May 2004
PDF: 11 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.536254
Show Author Affiliations
Toshiya Kotani, Toshiba Corp. (Japan)
Satoshi Tanaka, Toshiba Corp. (Japan)
Shigeki Nojima, Toshiba Corp. (Japan)
Koji Hashimoto, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)
Ichiro Mori, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

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