Share Email Print

Proceedings Paper

Patterning sub-50-nm Fin-FET using KrF lithography tool
Author(s): Navab Singh; S. Jagar; Sohan Singh Mehta; Moitreyee Mukherjee Roy; Rakesh Kumar; N. Balasubramanian
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A method to fabricate a very thin channel body Fin-FET and Tri-gate MOSFET is presented. 8% Attenuated Phase-shift mask (APSM) and single phase chrome-less mask (CLM) techniques are evaluated to pattern fins in sub-50 nm regime using KrF lithography scanner with a maximum numerical aperture of 0.68. Some of the issues of single phase CLM technique with respect to fin patterning are highlighted. Dual Exposure With Shift (DEWS)’ is introduced to pattern gate lines down to 80 nm using binary mask.

Paper Details

Date Published: 3 May 2004
PDF: 8 pages
Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.536040
Show Author Affiliations
Navab Singh, Institute of Microelectronics (Singapore)
S. Jagar, Institute of Microelectronics (Singapore)
Sohan Singh Mehta, Institute of Microelectronics (Singapore)
Moitreyee Mukherjee Roy, Institute of Microelectronics (Singapore)
Rakesh Kumar, Institute of Microelectronics (Singapore)
N. Balasubramanian, Institute of Microelectronics (Singapore)

Published in SPIE Proceedings Vol. 5379:
Design and Process Integration for Microelectronic Manufacturing II
Lars W. Liebmann, Editor(s)

© SPIE. Terms of Use
Back to Top