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Proceedings Paper

Minimizing critical layer systematic alignment errors during non-dedicated processing
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Paper Abstract

For the 150 nm and smaller half-pitch geometries, many DRAM manufacturers frequently employ dedicated exposure tool strategy for processing of most critical layers. Individual die tolerances of less than 40 nm are not uncommon for such compact geometries and a method is needed to reduce systematic overlay errors. The dedication strategy relies on the premise that a component of the systematic error induced by the inefficiencies in the exposure tool encountered at a specific layer can be diminished by re-exposing subsequent layer(s) on the same tool thus canceling out a large component of this error. In the past this strategy has, in general, resulted in better overall alignment performance, better exposure tool modeling and in decreased residual modeling errors. Increased alignment performance due to dedication does not come without its price. In such a dedicated strategy wafers are committed to process on the same tool at subsequent lithographic layers thus decreasing manufacturing flexibility and in turn affecting cost through increased processing cycle time. Tool down-events and equipment upgrades requiring significant downtime can also have a significant negative impact on running of a factory. This paper presents volume results for the 140 nm and 110 nm half-pitch geometries using 248 nm and 193 nm respective exposure wavelength state-of-art systems that show that dedicated processing still produces superior overlay and device performance results when compared blindly against non-dedicated processing. Results are also shown that at a given time an acceptable match may be found producing near equivalent results for non-dedicated processing. Changes in alignment capability are also observed after major equipment maintenance and component replacement. A point-in-time predictor strategy utilizing residual modeling errors and a set of modified performance specifications is directly compared against measured overlay data after patterning, against within field AFOV measurements after etching of the pattern and to final device performance.

Paper Details

Date Published: 28 May 2004
PDF: 9 pages
Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); doi: 10.1117/12.535248
Show Author Affiliations
Igor Jekauc, Infineon Technologies AG (United States)
William R. Roberts, Infineon Technologies AG (United States)

Published in SPIE Proceedings Vol. 5377:
Optical Microlithography XVII
Bruce W. Smith, Editor(s)

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