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Proceedings Paper

Test of a new sub-90-nm DR overlay mark for DRAM production
Author(s): Stefan Gruss; Ansgar Teipel; Carsten Fuelber; Elyakim Kassel; Mike Adel; Mark Ghinovker; Pavel Izikson
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Paper Abstract

An improved overlay mark design was applied in high end semiconductor manufacturing to increase the total overlay measurement accuracy with respect to the standard box-in-box target. A comprehensive study has been conducted on the basis of selected front-end and back-end DRAM layers (short loop) to characterize contributors to overlay error. This analysis is necessary to keep within shrinking overlay budget requirements.

Paper Details

Date Published: 24 May 2004
PDF: 12 pages
Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.534518
Show Author Affiliations
Stefan Gruss, Infineon Technologies AG (Germany)
Ansgar Teipel, Infineon Technologies AG (Germany)
Carsten Fuelber, Infineon Technologies AG (Germany)
Elyakim Kassel, KLA-Tencor Corp. (Israel)
Mike Adel, KLA-Tencor Corp. (Israel)
Mark Ghinovker, KLA-Tencor Corp. (Israel)
Pavel Izikson, KLA-Tencor Corp. (Israel)

Published in SPIE Proceedings Vol. 5375:
Metrology, Inspection, and Process Control for Microlithography XVIII
Richard M. Silver, Editor(s)

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