Share Email Print

Proceedings Paper

200-Mbps optical integrated circuit design and first iteration realizations in 1.2- and 0.8-micron Bi-CMOS technology
Author(s): Lukas Willem Snyman; C.-T. Chaing; Alfons Bogalecki; Monuko Du Plessis; Herzl Aharoni
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A prototype Silicon CMOS Optical Integrated Circuit (Si CMOS OEIC) was designed and simulated using standard 0.8 micron Bi-CMOS silicon integrated circuit technology. The circuit consisted of an integrated silicon light emitting source, an optical wave-guiding structure, two integrated optical detectors and two high-gain CMOS transimpedance analogue amplifiers. Simulations with MicroSim PSpice software predict a utilizable bandwidth capability of up to 220 MHz for the trans-impedance amplifier for detected photo-currents at the input of the amplifier in the range of 1 nA to 100 nA and driving a 10mV to 1 V signal into a 100 kΩ load. First iteration OEIC structures were realised in 1.2 micron CMOS technology for various source-waveguide-detector arrangements. Current signal ranging from 1nA to 1 micro-amp was detected at detectors. The technology seems favorable for first-iteration implementation for digital communications on chip up to 200Mbps.

Paper Details

Date Published: 1 July 2004
PDF: 10 pages
Proc. SPIE 5357, Optoelectronic Integration on Silicon, (1 July 2004); doi: 10.1117/12.530733
Show Author Affiliations
Lukas Willem Snyman, Technikon Pretoria (South Africa)
French South African Technical Institute in Electronics (South Africa)
C.-T. Chaing, Univ. of Pretoria (South Africa)
Alfons Bogalecki, Univ. of Pretoria (South Africa)
Monuko Du Plessis, Univ. of Pretoria (South Africa)
Herzl Aharoni, Univ. of Pretoria (South Africa)

Published in SPIE Proceedings Vol. 5357:
Optoelectronic Integration on Silicon
David J. Robbins; Ghassan E. Jabbour, Editor(s)

© SPIE. Terms of Use
Back to Top