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Proceedings Paper

Design of high-performance coprocessor for color error diffusion
Author(s): Philip P. Dang
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Paper Abstract

In this paper, we present an architecture of a color halftoning coprocessor. The design is based on a software/hardware design approach in which the flexibility and adaptability of the programmable processor and the high performance, low power of ASIC design are utilized. We employ the concurrency and locality concepts in computer architecture to address the computational intensive and data intensive issues of the color halftoning algorithm. Both instruction parallelism and data parallelism are exploited to speed up the performance. In addition, the fine-grain and middle-grain instruction level parallelism (ILP) are utilized to accelerate the computation in the color error diffusion halftoning process.

Paper Details

Date Published: 18 December 2003
PDF: 11 pages
Proc. SPIE 5293, Color Imaging IX: Processing, Hardcopy, and Applications, (18 December 2003); doi: 10.1117/12.527238
Show Author Affiliations
Philip P. Dang, STMicroelectronics Inc. (United States)

Published in SPIE Proceedings Vol. 5293:
Color Imaging IX: Processing, Hardcopy, and Applications
Reiner Eschbach; Gabriel G. Marcu, Editor(s)

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