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Proceedings Paper

Video processing on a flexible heterogeneous architecture
Author(s): Erwin B. Bellers; Johan G. W. M. Janssen; Selliah Rathnam
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Paper Abstract

Video Processing algorithms, and in particular those found in high-end television receivers, often have challenging demands for system resources. Therefore, most often, dedicated IC solutions are proposed to meet both the system and economic constraints. However as the functional requirements increase and as more diversity in terms of application support is required, dedicated solutions become less economic attractive, and hence a more heterogeneous architecture becomes more economic. In this paper, we present an architecture that is suited to run multiple very demanding video processing applications in real-time for consumer market applications.

Paper Details

Date Published: 19 April 2004
PDF: 10 pages
Proc. SPIE 5309, Embedded Processors for Multimedia and Communications, (19 April 2004); doi: 10.1117/12.527223
Show Author Affiliations
Erwin B. Bellers, Philips Semiconductors (United States)
Johan G. W. M. Janssen, Philips Semiconductors (United States)
Selliah Rathnam, Philips Semiconductors (United States)

Published in SPIE Proceedings Vol. 5309:
Embedded Processors for Multimedia and Communications
Subramania I. Sudharsanan; Michael Bove Jr.; Sethuraman Panchanathan, Editor(s)

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