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Proceedings Paper

High-performance low-power BinDCT coprocessor for wireless video applications
Author(s): Philip P. Dang; Truong Q. Nguyen; Trac D. Tran
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Paper Abstract

This paper presents an efficient VLSI architecture and a low complexity implementation of BinDCT coprocessor for wireless video application. The coprocessor architecture was implemented in VHDL and was synthesized with 0.18 mm CMOS technology. The footprint of the 2-D BinDCT coprocessor, which includes memory buffer, is 0.1173 mm2. The BinDCT coprocessor can calculate video in CIF format at 30 frames per second at 5 MHz clock rate with 1.55-volt power supply. The BinDCT coprocessor dissipates 12.05 mW. With its fast transform, compact size and low power consumption, the BinDCT coprocessor is an excellent candidate for DCT-based wireless multimedia coding systems.

Paper Details

Date Published: 18 May 2004
PDF: 10 pages
Proc. SPIE 5297, Real-Time Imaging VIII, (18 May 2004); doi: 10.1117/12.525128
Show Author Affiliations
Philip P. Dang, STMicroelectronics Inc. (United States)
Truong Q. Nguyen, Univ. of California/San Diego (United States)
Trac D. Tran, Johns Hopkins Univ. (United States)


Published in SPIE Proceedings Vol. 5297:
Real-Time Imaging VIII
Nasser Kehtarnavaz; Phillip A. Laplante, Editor(s)

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