We specifically studied the influence of a setback-layer thickness on the device performances so as to optimize the required value. Theoretical analysis shows that an optimized setback-layer thickness is available to effectively reduce the barrier height while maintain good device performances. In this work, the effects of a setback-layer thickness on the DC and RF performances of an InGaP/GaAs heterojunction bipolar transistor (HBT) are investigated. Based on the theoretical analysis, the optimized setback-layer thickness WSB is about of 10~30Å for analog amplification. On the other hand, for digital saturated logic application, i.e., a small offset voltage with an acceptable current gain, the optimized W_SB could be up to 50 Å. Therefore, this analysis and predication may cause the considerable promise for practical circuit applications.

Date Published: 2 April 2004
PDF: 8 pages
Proc. SPIE 5276, Device and Process Technologies for MEMS, Microelectronics, and Photonics III, (2 April 2004); doi: 10.1117/12.522286

Published in SPIE Proceedings Vol. 5276:
Device and Process Technologies for MEMS, Microelectronics, and Photonics III
Jung-Chih Chiao; Alex J. Hariz; David N. Jamieson; Giacinta Parish; Vijay K. Varadan, Editor(s)