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Proceedings Paper

200-mm EPL stencil mask fabrication by using SOI substrate
Author(s): Hiroshi Sugimura; Hideyuki Eguchi; Takashi Yoshii; Akira Tamura
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Paper Abstract

We developed 200-mm stencil masks for electron projection lithography (EPL) by using silicon-on-insulator (SOI) substrates. Stress of a 2-μm-thick single crystalline silicon membrane, where patterns were fabricated as openings, was controlled around 10 MPa by adjusting concentration of impurities doped into the SOI layer. Boron and phosphorus were investigated as doping impurities, and it was confirmed that doping both elements were capable of stress control. For forming struts that supported the thin membrane, a time multiplexed etch method was applied. Control of the deep etch parameters made it possible for the SiO2 stopper layer not to be etched through even if its thickness was sub-microns. To fabricate pattern openings in the membrane, reactive ion etching with high-density plasma was applied and lines down to 140 nm was fabricated in a 200-mm mask. Image placement distortion within a subfield was measured across the 200-mm mask and magnitudes of the image placement distortion were typically ~15 nm (3σ). A 200-mm EPL stencil mask having Selete's actual 70-nm design-rule system on chip (SoC) device pattern was successfully fabricated. We confirmed that the SOI substrates had potential abilities as initial material for 200-mm stencil mask fabrication.

Paper Details

Date Published: 28 August 2003
PDF: 9 pages
Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); doi: 10.1117/12.504246
Show Author Affiliations
Hiroshi Sugimura, Toppan Printing Co., Ltd. (Japan)
Hideyuki Eguchi, Toppan Printing Co., Ltd. (Japan)
Takashi Yoshii, Toppan Printing Co., Ltd. (Japan)
Akira Tamura, Toppan Printing Co., Ltd. (Japan)

Published in SPIE Proceedings Vol. 5130:
Photomask and Next-Generation Lithography Mask Technology X
Hiroyoshi Tanabe, Editor(s)

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