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Proceedings Paper

High-speed hardware architecture for high-definition videotex system
Author(s): Mitsuru Maruyama; Hiroaki Sakamoto; Yutaka Ishibashi; Kazutoshi Nishimura
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Paper Abstract

An experimental high-definition videotex system for broadband ISDN has been developed, and this paper introduces high-speed hardware architecture for this system. Key technologies required are highspeed protocol processing, high-speed data transfer, and high-speed picture readout. High-speed protocol processing — using a newly developed virtual memory copy, contents rearrangement memory, two-bus architecture, and simultaneous editing and analyzing — allows a requested 6-MB picture to be displayed within 3 seconds.

Paper Details

Date Published: 1 November 1991
PDF: 12 pages
Proc. SPIE 1605, Visual Communications and Image Processing '91: Visual Communication, (1 November 1991); doi: 10.1117/12.50267
Show Author Affiliations
Mitsuru Maruyama, NTT Human Interface Labs. (Japan)
Hiroaki Sakamoto, NTT Human Interface Labs. (Japan)
Yutaka Ishibashi, NTT Human Interface Labs. (Japan)
Kazutoshi Nishimura, NTT Human Interface Labs. (Japan)

Published in SPIE Proceedings Vol. 1605:
Visual Communications and Image Processing '91: Visual Communication
Kou-Hu Tzou; Toshio Koga, Editor(s)

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