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Proceedings Paper

Scheduling components for multigigabit network SoCs
Author(s): Theofanis Orphanoudakis; George Kornaros; Ioannis Papaefstathiou; Helen-Catherine Leligou; Stylianos Perissakis; Nicholas Zervos
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Paper Abstract

To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, great emphasis is placed on unconventional hardware architectures of network processors. This paper analyzes the problem of processor internal resource and traffic management and proposes a programmable scheduler architecture implemented in a novel protocol processor that deals with the above problems in an integrated way. We briefly outline the architecture of the protocol processor and we support that the innovative scheduling scheme integrated in PRO3 is, in general, crucial for network Systems-on-Chip since it makes it feasible to use scheduler's architecture are discussed that lead to efficient integration of the component to different network processor architectures at a similar cost. Its beneficial features are easy hardware implementation, low memory bandwidth requirements and high flexibility so as to support multiple service disciplines in a programmable way, thousands of flows and even perform different scheduling tasks.

Paper Details

Date Published: 21 April 2003
PDF: 12 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498488
Show Author Affiliations
Theofanis Orphanoudakis, Ellemedia Technologies (Greece)
George Kornaros, Ellemedia Technologies (Greece)
Ioannis Papaefstathiou, Foundation for Research and Technology-Hellas (Greece)
Helen-Catherine Leligou, National Technical Univ. of Athens (Greece)
Stylianos Perissakis, Ellemedia Technologies (Greece)
Nicholas Zervos, Ellemedia Technologies (Greece)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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