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Proceedings Paper

Impact of scaling down on 1/f noise in MOSFETs
Author(s): Matteo Valenza; Alain Hoffmann; Arnaud Laigle; Dominique Rigaud; Mathieu Marin
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Paper Abstract

An overview of the theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependence of 1/f noise in all conduction regime are summarized. Recent experimental studies on 1/f noise in MOS transistors are presented with special emphasis for PMOS from a 90 nm CMOS technology. Gate and drain noise sources are investigated. It is shown that in subthreshold regime drain current noise agrees with carrier number fluctuation model whereas in strong inversion the evolutions can be described by mobility fluctuation model. Gate current noise shows 1/f and white noise. White noise is very close to shot noise, and we have a quadratic variation of 1/f noise with gate current. Coherence measurements show that the increase of drain noise at high gate biases can be attributed to tunneling effects. Input-referred gate noise and the volume trap density can be used as figure of merit. Discrepancies with the ITRS roadmap are discussed.

Paper Details

Date Published: 12 May 2003
PDF: 15 pages
Proc. SPIE 5113, Noise in Devices and Circuits, (12 May 2003); doi: 10.1117/12.492906
Show Author Affiliations
Matteo Valenza, Univ. Montpellier II (France)
Alain Hoffmann, Univ. Montpellier II (France)
Arnaud Laigle, Univ. Montpellier II (France)
Dominique Rigaud, Univ. Montpellier II (France)
Mathieu Marin, STMicroelectronics (France)

Published in SPIE Proceedings Vol. 5113:
Noise in Devices and Circuits
M. Jamal Deen; Zeynep Celik-Butler; Michael E. Levinshtein, Editor(s)

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