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Proceedings Paper

Honeywell's submicron polysilicon gate process
Author(s): Lap S. Chan; Craig K. Hertog; D. W. Youngner
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Paper Abstract

This paper describes a manufacturable submicron CMOS polysilicon gate process. A new hydrogen bromide (HBr) plasma chemistry for etching and contrast enhancement material (CEM) for optical lithography have been applied. The HBr chemistry has achieved a selectivity of better than 30: 1 to gate oxide with a vertical side wall profile and no measurable undercutting even with POC13 doped poiy. Because of the low etch rate of photoresist and the CEM process the size change during etch (pre vs. post ) is estimated to be less than O. 05p. per side. In addition the multilayer contrast enhanced photoresist process has been optimized using statistically designed experiments to achieve maximum critical dimension (CD) control resolution and depth of focus. Electrical line width studies show that the total proximity effect due to lithography and etch is about O. O4t. Statistical process control of O. 8O. i. O. 15p. (3) has been achieved and demonstrated on Honeywell''s O. 8p. Radiation Hardened CMOS technology

Paper Details

Date Published: 1 March 1991
PDF: 8 pages
Proc. SPIE 1392, Advanced Techniques for Integrated Circuit Processing, (1 March 1991); doi: 10.1117/12.48917
Show Author Affiliations
Lap S. Chan, Honeywell Solid State Electronics Ctr. (United States)
Craig K. Hertog, Honeywell Solid State Electronics Ctr. (United States)
D. W. Youngner, Honeywell Solid State Electronics Ctr. (United States)

Published in SPIE Proceedings Vol. 1392:
Advanced Techniques for Integrated Circuit Processing
James A. Bondur; Terry R. Turner, Editor(s)

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