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Proceedings Paper

1/f noise and clock jitter in digital electronic systems
Author(s): Leonard Forbes; C.W. Zhang
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Paper Abstract

Timing jitter is a concern in high speed digital integrated circuits, the presence of timing jitter will degrade system performance in many high-speed applications. In the first part of this paper, we have simulated the timing jitter due to CMOS device noise in a nine stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results show the variation of absolute jitter due to flicker noise has a linear time dependence, while for white noise it has a square root time dependence, these are consistent with accepted theory. Two important parameters cycle jitter, and cycle to cycle jitter used to describe jitter performance can be obtained from simulation. Simulation results are also compared to experimental results. The methodology developed described in this paper is also applicable to other types of clock generators and oscillators such as LC oscillators, as well as other kinds of noise sources as power supply and substrate noise. In the second part this paper, we have employed this methodology and investigated the timing jitter in silicon BJT /or SiGe HBT ECL ring oscillators, and we have shown BJT /or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. As such silicon BJT and/or SiGe HBT ring oscillators are a potential choice for low jitter applications.

Paper Details

Date Published: 12 May 2003
PDF: 11 pages
Proc. SPIE 5113, Noise in Devices and Circuits, (12 May 2003); doi: 10.1117/12.488153
Show Author Affiliations
Leonard Forbes, Oregon State Univ. (United States)
C.W. Zhang, Oregon State Univ. (United States)

Published in SPIE Proceedings Vol. 5113:
Noise in Devices and Circuits
M. Jamal Deen; Zeynep Celik-Butler; Michael E. Levinshtein, Editor(s)

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