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Proceedings Paper

OPC on real-world circuitry
Author(s): Sean C. O'Brien; Tom Aton; Mark E. Mason; Carl Vickery; John N. Randall
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Paper Abstract

In the face of Moore's Law, the lithographic community is finding increasing pressure to do more with less. More, in the sense that lithographers are expected to use an exposure wavelength "lambda" that is shrinking at a slower rate than the critical dimensions (CDs) of devices. This has resulted in the introduction of complicated Resolution Enhancement Technology (RET) schemes. Less, in the sense that the competitive marketplace has resulted in shortened development cycles. These shortened development times mean that lithography and RET teams are often expected to demonstrate "first pass success" with increasing complex lithographic solutions. Unfortunately, first silicon on product prototypes may reveal deficiencies in an OPC infrastrcuture which had been developed using only research and development (R&D) testdie. The primary cause of these deficiencies is that the development and test-structure layouts frequently lack the 2D complexity of real circuitry. OPC models and lithography R&D traditionally compensate well for failures and marginal sites on the simple patterns of R&D testdie. The more complex geometries of real layouts frequently present new challenges. Here, we describe a program initiated at TI to add a complex pattern to the very first test reticle generated for a new technology node. This pattern is auto-generated and includes a random combination of representive circuits at the design rule for that node. OPC is applied to the pattern almost immediately after layout. The distribtion of printed features and marginal sites can then be identified early using simulation. Scanning Electron Microscope (SEM) images of resist and post-etch features can further identify sites requiring changes once reticles are received. We have shown that this early OPC R&D on complex geometries can prevent several OPC revision cycles and enable faster volume yield ramp.

Paper Details

Date Published: 10 July 2003
PDF: 9 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.485484
Show Author Affiliations
Sean C. O'Brien, Texas Instruments Inc. (United States)
Tom Aton, Texas Instruments Inc. (United States)
Mark E. Mason, Texas Instruments Inc. (United States)
Carl Vickery, Texas Instruments Inc. (United States)
John N. Randall, Zyvex Corp. (United States)


Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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