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Proceedings Paper

Model-assisted placement of subresolution assist features: experimental results
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Paper Abstract

Lithography models calibrated from experimental data have been used to determine the optimum insertion strategy of sub-resolution assist features in a 130 nm process. This work presents results for 3 different illumination types: Standard, QUASAR, and Annular. The calibrated models are used to classify every edge in the design based on its optical properties (in this case image-log-slope). This classification is used to determine the likelihood of an edge to print on target with the maximum image-log-slope. In other words, the method classifies design edges not in geometrically equivalent classes, but according to equivalent optical responses. After all the edges are classified, a rule table is generated for every process. This table describes the width and separation of the assist features based on a global cost function for each illumination type. The tables are later used to insert the assist features of various widths and separations using pre-defined priority strategies. After the bars have been inserted, OPC is applied to the main structures in the presence of the newly added assist features. Critical areas are tagged for increased fragmentation allowing certain areas to receive the maximum amount of correction and compensate for any proximity effects due to the sub-resolution assist features. The model-assisted solution is compared against a traditional rule-based solution, which was also derived experimentally. Both scenarios have model based OPC correction applied using simulation and experimental data. By comparing both cases it is possible to assess the advantages and disadvantages of both methods.

Paper Details

Date Published: 10 July 2003
PDF: 8 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.485421
Show Author Affiliations
Travis E. Brist, LSI Logic Corp. (United States)
Juan Andres Torres, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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