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Proceedings Paper

Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-um CMOS technology
Author(s): Tzy-Kuang Lee; Yao-Ching Wang; Min-hwa Chi; C. Y. Lu; C. H. Hsieh; R. G. Liu; H. J. Liao; S. S. Yang; Chih-Hao Chang
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Paper Abstract

The yield impact by local non-uniformity of poly-gate CD, edge profile, and transistor performance (between larger pitch area and minimum pitch area) is no longer tolerable in advanced CMOS technology as illustrated in a 2M SRAM vehicle processed by 0.13um flow in this paper. Micro-loading effects shall be minimized for process steps in poly-gate loop (including poly patterning, hard-mask etching, photo-resist (PR) ashing, poly etching, hard-mask removal, wet clean, etc), so that the accumulated local non-uniformity can be minimized. Also additional OPC may be applied locally (on mask) to compensate the remaining local non-uniformity. Significantly higher yield of a vehicle (2M SRAM) is demonstrated by efforts from both minimizing micro-loading effect in process steps as well as applying additional local OPC.

Paper Details

Date Published: 26 June 2003
PDF: 7 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (26 June 2003); doi: 10.1117/12.485250
Show Author Affiliations
Tzy-Kuang Lee, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Yao-Ching Wang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Min-hwa Chi, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
C. Y. Lu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
C. H. Hsieh, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
R. G. Liu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
H. J. Liao, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
S. S. Yang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chih-Hao Chang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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