
Proceedings Paper
Optimization of align marks and overlay targets in VIA first dual damascene processFormat | Member Price | Non-Member Price |
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Paper Abstract
Due to its low resistance and high electromigration performance, copper is now considered as a better metalization than the currently used aluminum based alloys. Dual damascene architecture is generally proposed for fabrication of multilevel copper interconnection. However, in the case of via first dual damascene scheme, we have great difficulties in M2 Trench photoprocess such as alignments and overlay measurements because this scheme makes too high topography of via patterns. Alignment marks and overlay targets made during via patterning process do not have good image contrasts after coating BARC and photoresist. Deteriorated image contrast of alignment marks and overlay targets increases the uncertainty in the alignment and overlay measurement. The image contrasts of alignment mark become worse after coating BARC and photoresist, resulting in weak, noisy, and asymmetric alignment signals. In this paper, we evaluated the impacts of mark structure, geometry, and BARC processing for the alignments and the overlay measurements using convex or concave structures, bar or slit structures, and special designed structures in M2 trench photo process. We also investigated the copper filled keys on M1 trench layer as alternative alignment targets.
Paper Details
Date Published: 2 June 2003
PDF: 13 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.485032
Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)
PDF: 13 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.485032
Show Author Affiliations
Dae-Ung Shin, Hynix Semiconductor Inc. (South Korea)
Young-Bae Jeong, Hynix Semiconductor Inc. (South Korea)
Jeong-Lyeol Park, Hynix Semiconductor Inc. (South Korea)
Young-Bae Jeong, Hynix Semiconductor Inc. (South Korea)
Jeong-Lyeol Park, Hynix Semiconductor Inc. (South Korea)
Jae-Sung Choi, Hynix Semiconductor Inc. (South Korea)
Jeong-Gun Lee, Hynix Semiconductor Inc. (South Korea)
Dae-Hoon Lee, Hynix Semiconductor Inc. (South Korea)
Jeong-Gun Lee, Hynix Semiconductor Inc. (South Korea)
Dae-Hoon Lee, Hynix Semiconductor Inc. (South Korea)
Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)
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